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Quad 64-/256-Position I2C Nonvolatile Memory Digital Potentiometers AD5253/AD5254
FEATURES
AD5253: Quad 64-position resolution AD5254: Quad 256-position resolution 1 k, 10 k, 50 k, 100 k Nonvolatile memory1 stores wiper settings with write protection Power-on refreshed to EEMEM settings in 300 s typ EEMEM rewrite time = 540 s typ Resistance tolerance stored in nonvolatile memory 12 extra bytes in EEMEM for user-defined information I2C(R) compatible serial interface Direct read/write accesses of RDAC2 and EEMEM registers Predefined linear increment/decrement commands Predefined 6 dB step change commands Synchronous or asynchronous quad channel update Wiper setting readback 4 MHz bandwidth--1 k version Single supply 2.7 V to 5.5 V Dual supply 2.25 V to 2.75 V 2 slave address decoding bits allow operation of 4 devices 100-year typical data retention, TA = 55C Operating temperature: -40C to +85C
VDD VSS DGND WP SCL SDA DATA I2C SERIAL INTERFACE RDAC1 REGISTER RDAC1 A1 W1 B1 RDAC2 RDAC2 REGISTER A2 W2 B2 RDAC3
FUNCTIONAL BLOCK DIAGRAM
RDAC EEMEM EEMEM POWER-ON REFRESH RAB TOL RDAC0 REGISTER RDAC0 A0 W0 B0
CONTROL COMMAND DECODE LOGIC ADDRESS DECODE LOGIC CONTROL LOGIC
AD0 AD1
AD5253/AD5254
RDAC3 REGISTER
A3 W3 B3
03824-0-001
Figure 1.
APPLICATIONS
Mechanical potentiometer replacement Low resolution DAC replacement RGB LED backlight control White LED brightness adjustment RF base station power amp bias control Programmable gain and offset control Programmable attenuators Programmable voltage-to-current conversion Programmable power supply Programmable filters Sensor calibrations
The AD5253/AD5254 allow the host I2C controllers to write any of the 64-/256-step wiper settings in the RDAC registers and store them in the EEMEM. Once the settings are stored, they are restored automatically to the RDAC registers at system poweron; the settings can also be restored dynamically. The AD5253/AD5254 provide additional increment, decrement, +6 dB step change, and -6 dB step change in synchronous or asynchronous channel update modes. The increment and decrement functions allow stepwise linear adjustments, while 6 dB step changes are equivalent to doubling or halving the RDAC wiper setting. These functions are useful for steep-slope nonlinear adjustment applications such as white LED brightness and audio volume control. The AD5253/AD5254 have a patented resistance tolerance storing function that allows the user to access the EEMEM and obtain the absolute end-to-end resistance values of the RDACs for precision applications. The AD5253/AD5254 are available in TSSOP-20 packages in 1 k, 10 k, 50 k, and 100 k options. All parts are guaranteed to operate over the -40C to +85C extended industrial temperature range.
GENERAL DESCRIPTION
The AD5253/AD5254 are quad channel, I2C, nonvolatile memory, digitally controlled potentiometers with 64/256 positions, respectively. These devices perform the same electronic adjustment functions as mechanical potentiometers, trimmers, and variable resistors. The AD5253/AD5254's versatile programmability allows multiple modes of operation, including read/write accesses in the RDAC and EEMEM registers, increment/decrement of resistance, resistance changes in 6 dB scales, wiper setting readback, and extra EEMEM for storing user-defined information, such as memory data for other components, look-up table, or system identification information.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
1 2
The terms nonvolatile memory and EEMEM are used interchangeably. The terms digital potentiometer and RDAC are used interchangeably.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
AD5253/AD5254 TABLE OF CONTENTS
Electrical Characteristics ................................................................. 3 1 k Version.................................................................................. 3 10 k, 50 k, 100 k Versions ................................................... 5 Interface Timing Characteristics (All Parts)............................. 7 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Pin Configuration and Functional Descriptions.......................... 9 Typical Performance Characteristics ........................................... 10 I2C Interface..................................................................................... 14 I2C Interface General Description............................................ 14 I2C Interface Detail Description ............................................... 15 I2C Compatible 2-Wire Serial Bus............................................ 19 Theory of Operation ...................................................................... 20 Linear Increment and Decrement Commands ...................... 20 6 dB Adjustments (Doubling/Halving Wiper Setting)........ 20 Digital Input/Output Configuration........................................ 21 Multiple Devices On One Bus .................................................. 21 Terminal Voltage Operation Range ......................................... 22 Power-Up and Power-Down Sequences.................................. 22 Layout and Power Supply Biasing ............................................ 22 Digital Potentiometer Operation ............................................. 23 Programmable Rheostat Operation......................................... 23 Programmable Potentiometer Operation ............................... 24 Applications..................................................................................... 25 RGB LED LCD Backlight Controller....................................... 25 Outline Dimensions ....................................................................... 27 Ordering Guide .......................................................................... 27
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD5253/AD5254 ELECTRICAL CHARACTERISTICS
1 k VERSION
VDD = +3 V 10% or +5 V 10%, VSS = 0 V or VDD/VSS = 2.5 V 10%, VA = +VDD, VB = 0 V, -40C < TA < +85C, unless otherwise noted. Table 1.
Parameter Symbol DC CHARACTERISTICS--RHEOSTAT MODE Resolution N Resistor Differential Nonlinearity2 R-DNL Conditions AD5253/AD5254 RWB, RWA = NC, VDD = 5.5V, AD5253 RWB, RWA = NC, VDD = 5.5V, AD5254 RWB, RWA = NC, VDD = 2.7V, AD5253 RWB, RWA = NC, VDD = 2.7V, AD5254 RWB, RWA = NC, VDD = 5.5V, AD5253 RWB, RWA = NC, VDD = 5.5V, AD5254 RWB, RWA = NC, VDD = 2.7V, AD5253 RWB, RWA = NC, VDD = 2.7V, AD5254 TA = 25C Min Typ1 Max 6/8 +0.5 +1 +0.75 +1.5 +0.5 +2 +4 +14 +30 Unit Bits LSB LSB LSB LSB LSB LSB LSB LSB % ppm/C % LSB LSB LSB LSB ppm/C LSB LSB LSB LSB LSB LSB LSB LSB V pF pF
Resistor Nonlinearity2
R-INL
Nominal Resistor Tolerance Resistance Temperature Coefficient Wiper Resistance
RAB/RAB (RAB/RAB) x 106/T RW
-0.5 -1 -0.75 -1.5 -0.5 -2 -1 -2 -30
0.2 0.25 0.3 0.3 0.2 0.5 +2.5 +9
IW = 1 V/R, VDD = 5 V IW = 1 V/R, VDD = 3 V
Channel Resistance Matching RAB1/RAB2 DC CHARACTERISTICS--POTENTIOMETER DIVIDER MODE Differential Nonlinearity3 DNL Integral Nonlinearity3 Voltage Divider Temperature Coefficient Full-Scale Error INL
650 75 200 0.15 -0.5 -1 -0.5 -2 0.1 0.25 0.2 0.5 25 -3 -11 -4 -16 3 11 4 15
130 300
AD5253 AD5254 AD5253 AD5254 Code = Half scale Code = Full scale, VDD = 5.5 V, AD5253 Code = Full scale, VDD = 5.5 V, AD5254 Code = Full scale, VDD = 2.7 V, AD5253 Code = Full scale, VDD = 2.7 V, AD5254 Code = Zero scale, VDD = 5.5 V, AD5253 Code = Zero scale, VDD = 5.5 V, AD5254 Code = Zero scale, VDD = 2.7 V, AD5253 Code = Zero scale, VDD = 2.7 V, AD5254
+0.5 +1 +0.5 +2
(VW/VW) x 106/T VWFSE
Zero-Scale Error
VWZSE
-5 -16 -6 -23 0 0 0 0 VSS
0 0 0 0 5 16 6 20 VDD
RESISTOR TERMINALS Voltage Range4 Capacitance5 Ax, Bx Capacitance5 Wx Common-Mode Leakage Current DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Output Logic High (SDA) Output Logic Low (SDA) WP Leakage Current
VA, VB, VW CA, CB CW
f = 1 kHz, measured to GND, Code = Half scale f = 1 kHz, measured to GND, Code = Half scale VA = VB = VDD /2 VDD = 5 V, VSS = 0 V VDD/VSS = +2.7 V/0 V or VDD/VSS = 2.5 V VDD =5 V, VSS = 0 V VDD/VSS = +2.7 V/0 V or VDD/VSS = 2.5 V RPULL-UP = 2.2 k to VDD = 5 V, VSS = 0 V RPULL-UP = 2.2 k to VDD =5 V, VSS = 0 V WP = VDD 2.4 2.1
85 95
ICM VIH VIL VOH VOL IWP
0.01
1
A V V V V V V A
0.8 0.6 4.9 0.4 5
Rev. 0 | Page 3 of 28
AD5253/AD5254
Parameter Symbol DIGITAL INPUTS AND OUTPUTS (continued) A0 Leakage Current IA0 Input Leakage Current (Other than WP and A0) II Input Capacitance5 CI POWER SUPPLIES Single-Supply Power Range VDD Dual-Supply Power Range VDD/VSS Positive Supply Current IDD Negative Supply Current ISS EEMEM Data Storing Mode Current EEMEM Data Restoring Mode Current6 Power Dissipation7 Power Supply Sensitivity DYNAMIC CHARACTERISTICS5, 8 Bandwidth -3 dB Total Harmonic Distortion VW Settling Time Resistor Noise Voltage Digital Crosstalk Analog Coupling Conditions A0 = GND VIN = 0 V or VDD 5 VSS = 0 V VIH = VDD or VIL = GND VIH = VDD or VIL = GND, VDD = +2.5 V, VSS = -2.5 V VIH = VDD or VIL = GND VIH = VDD or VIL = GND VIH = VDD = 5 V or VIL = GND VDD = 5 V 10% VDD = 3 V 10% RAB = 1 k VA =1 V rms, VB = 0 V, f = 1 kHz VA = VDD, VB = 0 V RWB = 500 , f = 1 kHz. Thermal noise only. VA = VDD, VB = 0 V, measure VW with adjacent RDAC making full-scale change Signal input at A0 and measure the output at W1, f = 1 kHz 2.7 2.25 5 -5 5.5 2.75 15 -15 Min Typ1 Max 3 1 Unit A A pF V V A A
IDD_STORE IDD_RESTORE PDISS PSS
35 2.5 -0.025 -0.04 0.01 0.02 4 0.05 0.2 3 -80 -72 0.075 0.025 0.04
mA mA mW %/% %/% MHz % s nV/Hz dB dB
BW THD tS eN_WB CT CAT
Rev. 0 | Page 4 of 28
AD5253/AD5254
10 k, 50 k, 100 k VERSIONS
VDD = +3 V 10% or +5 V 10%, VSS = 0 V or VDD/VSS = 2.5 V 10%, VA = +VDD, VB = 0 V, -40C < TA < +85C, unless otherwise noted. Table 2.
Parameter Symbol DC CHARACTERISTICS--RHEOSTAT MODE Resolution N Resistor Differential R-DNL Nonlinearity2 Resistor Nonlinearity2 Nominal Resistor Tolerance Resistance Temperature Coefficient Wiper Resistance Channel Resistance Matching R-INL RAB/RAB (RAB/RAB) x 106/T RW Conditions AD5253/AD5254 RWB, RWA = NC, AD5253 RWB, RWA = NC, AD5254 RWB, RWA = NC, AD5253 RWB, RWA = NC, AD5254 TA = 25C -0.75 -1 -0.75 -2.5 -20 0.1 0.25 0.25 1 Min Typ1 Max 6/8 +0.75 +1 +0.75 +2.5 +20 Unit Bits LSB LSB LSB LSB % ppm/C % % +0.5 +1 +0.5 +1.5 LSB LSB LSB LSB ppm/C LSB LSB LSB LSB V pF pF
IW = 1 V/R, VDD = 5 V IW = 1 V/R, VDD = 3 V
650 75 200 0.15 0.05 -0.5 -1 -0.5 -1.5 0.1 0.3 0.15 0.5 15 -0.3 -1 0.3 1.2
130 300
RAB = 10 k, 50 k RAB = 100 k DC CHARACTERISTICS--POTENTIOMETER DIVIDER MODE Differential Nonlinearity3 DNL AD5253 AD5254 Integral Nonlinearity3 INL AD5253 AD5254 Voltage Divider Code = Half scale Temperature Coefficient (VW/VW) x 106/T Full-Scale Error VWFSE Code = Full scale, AD5253 Code = Full scale, AD5254 Zero-Scale Error VWZSE Code = Zero scale, AD5253 Code = Zero scale, AD5254 RESISTOR TERMINALS Voltage Range4 VA, VB, VW 5 Capacitance Ax, Bx CA, CB f = 1 kHz, measured to GND, Code = Half scale Capacitance5 Wx CW f = 1 kHz, measured to GND, Code = Half scale Common-Mode Leakage ICM VA = VB = VDD/2 Current6 DIGITAL INPUTS AND OUTPUTS Input Logic High VIH VDD = 5 V, VSS = 0 V VDD/VSS = +2.7 V/0 V or VDD/VSS = 2.5 V Input Logic Low VIL VDD = 5 V, VSS = 0 V VDD/VSS = +2.7 V/0 V or VDD/VSS = 2.5 V Output Logic High (SDA) VOH RPULL-UP = 2.2 k to VDD = 5 V, VSS = 0 V Output Logic Low (SDA) VOL RPULL-UP = 2.2 k to VDD = 5 V, VSS = 0 V IWP WP Leakage Current WP = VDD A0 Leakage Current IA0 A0 = GND Input Leakage Current (Other than WP and A0) VIN = 0 V or VDD II Input Capacitance5 CI POWER SUPPLIES Single-Supply Power Range VDD VSS = 0 V Dual-Supply Power Range VDD/VSS Positive Supply Current IDD VIH = VDD or VIL = GND RAB1/RAB2
Rev. 0 | Page 5 of 28
-1 -3 0 0 VSS
0 0 1 3 VDD
85 95
0.01 2.4 2.1
1
A V V V V V V A A A pF V V A
0.8 0.6 4.9 0.4 5 3 1 5 2.7 2.25 5 5.5 2.75 15
AD5253/AD5254
Parameter POWER SUPPLIES (continued) Negative Supply Current EEMEM Data Storing Mode Current EEMEM Data Restoring Mode Current6 Power Dissipation7 Power Supply Sensitivity Symbol ISS Conditions VIH = VDD or VIL = GND, VDD = +2.5 V, VSS = -2.5 V VIH = VDD or VIL = GND, TA = 0C to 85C VIH = VDD or VIL = GND, TA = 0C to 85C VIH = VDD = 5 V or VIL = GND VDD = 5 V 10% VDD = 3 V 10% RAB = 10 k/50 k/100 k VA = 1 Vrms, VB = 0 V, f = 1 kHz VA = VDD, VB = 0 V, RAB = 10 k/50 k/100 k RAB = 10 k/50 k/100 k, Code = Midscale, f = 1 kHz. Thermal noise only. VA = VDD, VB = 0 V, Measure VW with adjacent RDAC making full scale change Signal input at A0 and measure output at W1, f = 1 kHz Min Typ1 -5 Max -15 Unit A
IDD_STORE IDD_RESTORE PDISS PSS
35 2.5 -0.005 -0.01 +0.002 +0.002 400/80/40 0.05 1.5/7/14 9/20/29 -80 -72 0.075 +0.005 +0.01
mA mA mW %/% %/% kHz % s nV/Hz dB dB
DYNAMIC CHARACTERISTICS5, 8 -3 dB Bandwidth BW Total Harmonic Distortion THDW VW Settling Time tS Resistor Noise Voltage Digital Crosstalk Analog Coupling eN_WB CT CAT
Rev. 0 | Page 6 of 28
AD5253/AD5254
INTERFACE TIMING CHARACTERISTICS (ALL PARTS)
Guaranteed by design, not subject to production test. See Figure 23 for location of measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using both VDD = 3 V and 5 V. When the part is not in operation, the SDA and SCL pins should be pulled high. When these pins are pulled low, the I2C interface at these pins conducts current of about 0.8 mA at VDD = 5.5 V and 0.2 mA at VDD = 2.7 V. Table 3.
Parameter SCL Clock Frequency tBUF Bus Free Time between STOP and START tHD;STA Hold Time (Repeated START) tLOW Low Period of SCL Clock tHIGH High Period of SCL Clock tSU;STA Setup Time for START Condition tHD;DAT Data Hold Time tSU;DAT Data Setup Time tF Fall Time of Both SDA and SCL Signals tR Rise Time of Both SDA and SCL Signals tSU;STO Setup Time for STOP Condition EEMEM Data Storing Time EEMEM Data Restoring Time at Power On9 EEMEM Data Restoring Time upon Restore Command or RESET Operation9 EEMEM Data Rewritable Time10 FLASH/EE MEMORY RELIABILITY Endurance11 Data Retention12 Symbol fSCL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 tEEMEM_STORE tEEMEM_RESTORE1 tEEMEM_RESTORE2 tEEMEM_REWRITE 100 100 Conditions Min 1.3 0.6 1.3 0.6 0.6 0 100 Typ1 Max 400 Unit kHz s s s s s s ns ns ns s ms s s s kCycles Years
After this period, the first clock pulse is generated
0.9 300 300
0.6 VDD rise time dependent. Measure without decoupling capacitors at VDD and VSS. VDD = 5 V 26 300 300 540
1 2
Typical values represent average readings at 25C and VDD = 5 V. Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5254 1 k version at VDD = 2.7V, IW = VDD/R for both VDD = 3 V or VDD = 5 V. 3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. 4 Resistor terminals A, B, and W have no limitations on polarity with respect to each other. 5 Guaranteed by design and not subject to production test. 6 cmd 0 NOP should be activated after cmd 1 in order to minimize IDD_RESTORE current consumption. 7 PDISS is calculated from (IDD x VDD = 5 V). 8 All dynamic characteristics use VDD = 5 V. 9 During power-up, all outputs preset to midscale before restoring EEMEM contents. RDAC0 has the shortest whereas RDAC3 has the longest EEMEM restore time. 10 Delay time after power-on or RESET before new EEMEM data to be written. 11 Endurance is qualified to 100,000 cycles per JEDEC Std. 22 method A117, and is measured at -40C, +25C, and +85C; typical endurance at +25C is 700,000 cycles. 12 Retention lifetime equivalent at junction temperature (TJ) = 55C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV derates with junction temperature.
Rev. 0 | Page 7 of 28
AD5253/AD5254 ABSOLUTE MAXIMUM RATINGS
Table 4. TA = 25C, unless otherwise noted
Parameter VDD to GND VSS to GND VDD to VSS VA, VB, VW to GND Maximum Current IWB, IWA Pulsed IWB Continuous (RWB 1 k, A Open)1 IWA Continuous (RWA 1 k, B Open)1 IAB Continuous (RAB = 1 k/10 k/50 k/100 k)1 Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJ MAX) Storage Temperature Lead Temperature (Soldering, 10 sec) Vapor Phase (60 sec) Infrared (15 sec) TSSOP-20 Thermal Resistance2 JA Rating -0.3 V, +7 V +0.3 V, -7 V 7V VSS, VDD 20 mA 5 mA 5 mA 5 mA/500 A/100 A/50 A 0 V, 7 V -40C to +85C 150C -65C to +150C 300C 215C 220C 143C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1
2
Maximum terminal current is bounded by the maximum applied voltage across any two of the A, B, and W terminals at a given resistance, the maximum current handling of the switches, and the maximum power dissipation of the package. VDD = 5V. Package power dissipation = (TJMAX - TA)/JA.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 8 of 28
AD5253/AD5254 PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
W0 1 B0 2 A0 3 AD0 4
10
VDD W3 B3
AD5253/ AD5254
9 8
7 A3 TOP VIEW WP 5 (Not to Scale) 6 AD1
W1 1 B1 2 A1 3 SDA 4 VSS 5
10 9 8 7 6
DGND SCL W2 B2 A2
03842-0-002
Figure 2. AD5253/AD5254 Pin Configuration
Table 5. AD5253/AD5254 Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Mnemonic W0 B0 A0 AD0 WP W1 B1 A1 SDA VSS A2 B2 W2 SCL DGND AD1 A3 B3 W3 VDD Description Wiper Terminal of RDAC0. VSS VW0 VDD. B Terminal of RDAC0. VSS VB0 VDD. A Terminal of RDAC0. VSS VA0 VDD. I2C Device Address 0. AD0 and AD1 allow four AD5253/AD5254s to be addressed. Write Protect, Active Low. VWP VDD + 0.3 V. Wiper Terminal of RDAC1. VSS VW1 VDD. B Terminal of RDAC1. VSS VB1 VDD. A Terminal of RDAC1. VSS VA1 VDD. Serial Data Input/Output Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first. Open-drain MOSFET requires pull-up resistor. Negative Supply. Connect to 0 V for single supply or -2.7 V for dual supply, where VDD - VSS +5.5 V. If VSS is used, rather than grounded, in dual supply, VSS must be able to sink 35 mA for 26 ms when storing data to EEMEM. A Terminal of RDAC2. VSS VA2 VDD. B Terminal of RDAC2. VSS VB2 VDD. Wiper Terminal of RDAC2. VSS VW2 VDD. Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges. VSCL (VDD + 0.3 V). Pull-up resistor is recommended for SCL to ensure minimum power. Digital Ground. Connect to system analog ground at a single point. I2C Device Address 1. AD0 and AD1 allow four AD5253/AD5254s to be addressed. A Terminal of RDAC3. VSS VA3 VDD. B Terminal of RDAC3. VSS VB3 VDD. W Terminal of RDAC3. VSS VW3 VDD. Positive Power Supply Pin. Connect +2.7 V to +5 V for single supply or 2.7 V for dual supply, where VDD - VSS 5.5 V. VDD must be able to source 35 mA for 26 ms when storing data to EEMEM.
Rev. 0 | Page 9 of 28
AD5253/AD5254 TYPICAL PERFORMANCE CHARACTERISTICS
1.0 0.8 0.6 0.4
R-INL (LSB)
1.0 0.8 TA = -40C, +25C, +85C, +125C
TA = -40C, +25C, +85C, +125C
0.6 0.4 0.2
0.2 0 -0.2 -0.4 -0.6 -0.8
03824-0-015
INL (LSB)
0 -0.2 -0.4 -0.6 -0.8
03824-0-018
-1.0 0 32 64 96 128 160 192 224 256 CODE (Decimal)
-1.0 0 32 64 96 128 160 192 224 256 CODE (Decimal)
Figure 3. R-INL vs. Code
Figure 6. DNL vs. Code
1.0 0.8 0.6 0.4
RDNL (LSB)
SUPPLY CURRENT (A)
10 TA = -40C, +25C, +85C, +125C 8 6 4 2 0 -2 -4 -6 -8
03824-0-016
03824-0-019
IDD @ VDD = +5.5V
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 32 64 96 128 160 192 224 256 CODE (Decimal)
IDD @ VDD = +2.7V
ISS @ VDD = +2.7V, VSS = -2.7V
-10 -40
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
Figure 4. R-DNL vs. Code
Figure 7. Supply Current vs. Temperature
1.0 0.8 0.6 0.4
INL (LSB)
10 TA = -40C, +25C, +85C, +125C 1 VDD = 5.5V
0 -0.2 -0.4 -0.6 -0.8
03824-0-017
IDD (mA)
0.2
0.1
0.01 VDD = 2.7V
0.001
0
32
64
96
128
160
192
224
256
0
1
2
3
4
5
6
CODE (Decimal)
DIGITAL INPUT VOLTAGE (V)
Figure 5. INL vs. Code
Figure 8. Supply Current vs. Digital Input Voltage. TA = 25C
Rev. 0 | Page 10 of 28
03824-0-020
-1.0
0.0001
AD5253/AD5254
240
POTENTIOMETER MODE TEMPCO (ppm/C)
30 DATA = 0x00 VDD = 2.7V TA = 25C VDD = 5V TA = -40C/+85C VA = VDD VB = 0V
220 200 180 160
RWB ()
25
20
140 120 100 80 60 40 20
03824-0-021
15
VDD = 5.5V TA = 25C
10
5
0
1
2
3 VBIAS (V)
4
5
6
0
32
64
96
128
160
192
224
256
CODE (Decimal)
Figure 9. Wiper Resistance vs. VBIAS
Figure 12. Potentiometer Mode Tempco (VWB/VWB)/T x 106 vs. Code
6
0 -6 0x40
0xFF 0x80
4
-12 -18
0x20 0x10
2
GAIN (dB)
RWB (%)
-24 -30 -36 -42 -48 0x08 0x04 0x02 0x01 0x00
0
-2
-4
-54
03824-0-025
03824-0-022
-6 -40
-60
-20
0
20
40
60
80
100
120
10
100
1k
10k
100k
1M
10M
TEMPERATURE (C)
FREQUENCY (Hz)
Figure 10. Change of RAB vs. Temperature
Figure 13. Gain vs. Frequency vs. Code, RAB = 1 k, TA = 25C
90
RHEOSTAT MODE TEMPCO (ppm/C)
0
0xFF 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x00 0x02
03824-0-026
80 70 60 50 40 30 20 10
VDD = 5V TA = -40C/+85C VA = VDD VB = 0V
GAIN (dB)
-6 -12 -18 -24 -30 -36 -42 -48 -54 -60
03824-0-023
0 0 32 64 96 128 160 192 224 256 CODE (Decimal)
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 11. Rheostat Mode Tempco (RWB/RWB)/T x 106 vs. Code
Figure 14. Gain vs. Frequency vs. Code, RAB = 10 k, TA = 25C
Rev. 0 | Page 11 of 28
03824-0-024
0
0
AD5253/AD5254
0 0xFF -6 -12 0x40 -18
GAIN (dB)
1.2 TA = 25C 1.0
0x80
0x20
IDD (mA)
0.8 VDD = 5.5V 0.6
-24 -30 -36 -42 -48 -54
0x10 0x08 0x04 0x02 0x01 0x00
03824-0-027
0.4
0.2
VDD = 2.7V
10
100
1k
10k
100k
1M
10M
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
CLOCK FREQUENCY (Hz)
Figure 15. Gain vs. Frequency vs. Code, RAB = 50 k, TA = 25C
Figure 18. Supply Current vs. Digital Input Clock Frequency
0 0x80 -6 -12 -18
GAIN (dB)
0xFF
CLK VDD = 5V
0x40 0x20 0x10 0x08 0x04 0x02
DIGITAL FEEDTHROUGH MID-SCALE TRANSITION 7FH 80H
-24 -30 -36 -42
VW
0x01 -48 -54
03824-0-028
-60 10 100 1k 10k 100k 1M FREQUENCY (Hz)
10M
Figure 16. Gain vs. Frequency vs. Code, RAB = 100 k, TA = 25C
Figure 19. Clock Feedthrough and Midscale Transition Glitch
100
VDD = 5.5V
80 100k 60 40 20 RAB () 1k 0 -20 50k -40 -60 -80
03824-0-029
10k
MIDSCALE PRESET
RESTORE RDAC0 SETTING TO 0xFF
VDD (NO DECOUPLING CAPS) VWB0 (0xFF STORED IN EEMEM) VWB3 (0xFF STORED IN EEMEM)
RESTORE RDAC3 SETTING TO 0xFF MIDSCALE PRESET VDD = VA0 = VA3 = 3.3V GND = VB0 = VB3
0
32
64
96
128
160
192
224
256
CODE (Decimal)
Figure 17. RAB vs. Code, TA = 25C
Figure 20. tEEMEM_RESTORE of RDAC0 and RDAC3
Rev. 0 | Page 12 of 28
03824-0-046
-100
03824-0-031
0x00
03824-0-030
-60
0
AD5253/AD5254
6 6
5 THEORETICAL IWB_MAX (mA)
RAB = 1k THEORETICAL IWB_MAX (mA)
5
RAB = 1k
4
VA = VB = OPEN TA = 25C
4
VA = VB = OPEN TA = 25C
3
3
2
RAB = 10k
2
RAB = 10k
1
RAB = 50k RAB = 100k
03824-0-033
1
RAB = 50k RAB = 100k 0 32 64 96 128 160 192 224 256
03824-0-034
0 0
0
8
16
24
32
40
48
56
64
CODE (Decimal)
CODE (Decimal)
Figure 21. IWB_MAX vs. Code (AD5253)
Figure 22. IWB_MAX vs. Code (AD5254)
Rev. 0 | Page 13 of 28
AD5253/AD5254 I2C INTERFACE
SCL
t8
t9
t6
t2
t3 t8 t9
t4
t5
t7
t10
P
S
P
Figure 23. I2C Interface Timing Diagram
I2C INTERFACE GENERAL DESCRIPTION
From Master to Slave From Slave to Master S = Start Condition. P = Stop Condition. A = Acknowledge (SDA Low). A = Not Acknowledge (SDA High). R/W = Read Enable at High; Write Enable at Low.
S
SLAVE ADDRESS (7-BIT)
R/W
A
INSTRUCTIONS (8-BIT)
A
DATA (8-BIT)
A/A
P
03842-0-004
0 WRITE
DATA TRANSFERRED (N BYTES + ACKNOWLEDGE)
Figure 24. I2C--Master Writing Data to Slave
S
SLAVE ADDRESS (7-BIT)
R/W
A
DATA (8-BIT)
A
DATA (8-BIT)
A
P
03842-0-005
1 READ
DATA TRANSFERRED (N BYTES + ACKNOWLEDGE)
Figure 25. I2C--Master Reading Data From Slave
S
SLAVE ADDRESS (7-BIT)
R/W
A
DATA
A/A
S
SLAVE ADDRESS
R/W
A
DATA
A/A
03842-0-003
SDA
t1
P
03842-0-006
READ OR WRITE
(N BYTES + ACKNOWLEDGE)
REPEATED START
READ OR WRITE
(N BYTES + ACKNOWLEDGE)
DIRECTION OF TRANSFER MAY CHANGE AT THIS POINT
Figure 26. I2C--Combined Write/Read
Rev. 0 | Page 14 of 28
AD5253/AD5254
I2C INTERFACE DETAIL DESCRIPTION
From Master to Slave From Slave to Master S = Start Condition. P = Stop Condition. A = Acknowledge (SDA Low). A = Not Acknowledge (SDA High). AD1, AD0 = I2C Device Address Bits. Must match with the logic states at Pins AD1, AD0. R/W= Read Enable Bit, Logic High/Write Enable Bit, Logic Low. CMD/REG = Command Enable Bit, Logic High/Register Access Bit, Logic Low. EE/RDAC = EEMEM Register, Logic High/RDAC Register, Logic Low. A4, A3, A2, A1, A0 = RDAC/EEMEM Register Addresses.
S
0
1
0
1
1
A D 1
A D 0
0
A
CMD/ REG
0
EE/ RDAC
A 4
A 3
A 2
A 1
A 0
A
DATA
A/ A
P
SLAVE ADDRESS 0 WRITE 0 REG
INSTRUCTIONS AND ADDRESS
(1 BYTE + ACKNOWLEDGE)
Figure 27. Single Write Mode
03842-0-007
S
0
1
0
1
1
A D 1
A D 0
0
A
CMD/ REG
0
EE/ RDAC
A 4
A 3
A 2
A 1
A 0
A
RDAC_N DATA
A
RDAC_N + 1 DATA
A/ A
P
SLAVE ADDRESS 0 WRITE 0 REG
INSTRUCTIONS AND ADDRESS
(N BYTE + ACKNOWLEDGE)
Figure 28. Consecutive Write Mode
Table 6. Addresses for Writing Data Byte Contents to RDAC Registers (R/W = 0, CMD/REG = 0, EE/RDAC = 0)
A4 0 0 0 0 0 : 0 A3 0 0 0 0 0 : 1 A2 0 0 0 0 1 : 1 A1 0 0 1 1 0 : 1 A0 0 1 0 1 0 : 1 RDAC RDAC0 RDAC1 RDAC2 RDAC3 Reserved Reserved Data Byte Description 6-/8-bit wiper setting (2 MSBs of AD5253 are X) 6-/8-bit wiper setting (2 MSBs of AD5253 are X) 6-/8-bit wiper setting (2 MSBs of AD5253 are X) 6-/8-bit wiper setting (2 MSBs of AD5253 are X)
Rev. 0 | Page 15 of 28
03842-0-008
AD5253/AD5254
RDAC/EEMEM Write
Setting the wiper position requires an RDAC write operation. The single write operation is shown in Figure 27, and the consecutive write operation is shown in Figure 28. In consecutive write operation, if the RDAC is selected and the address starts at 0, the first data byte goes to RDAC0, the second data byte goes to RDAC1, the third data byte goes to RDAC2, and the fourth data byte goes to RDAC3. This operation can be continued up to eight addresses with four unused addresses; it then loops back to RDAC0. If the address starts at any of the eight valid addresses, N, the data first goes to RDAC_N, RDAC_N + 1, and so on; it loops back to RDAC0 after the eighth address. The RDAC address is shown in Table 6. While the RDAC wiper setting is controlled by a specific RDAC register, each RDAC register corresponds to a specific EEMEM memory location, which provides nonvolatile wiper storage functionality. The addresses are shown in Table 7. The single and consecutive write operations also apply to EEMEM write operations. There are 12 nonvolatile memory locations, EEMEM4 to EEMEM15, where users can store 12 bytes of information such as memory data for other components, look-up table, or system identification information. In a write operation to the EEMEM registers, the device disables the I2C interface during the internal write cycle. Acknowledge polling, which is discussed later in the data sheet, is required to determine the completion of the write cycle. Table 7. Addresses for Writing (Storing) RDAC Settings and User-Defined Data to EEMEM Registers (R/W = 0, CMD/REG = 0, EE/RDAC = 1)
A4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Data Byte Description Store RDAC0 Setting to EEMEM01 Store RDAC1 Setting to EEMEM11 Store RDAC2 Setting to EEMEM21 Store RDAC3 Setting to EEMEM31 Store User Data to EEMEM4 Store User Data to EEMEM5 Store User Data to EEMEM6 Store User Data to EEMEM7 Store User Data to EEMEM8 Store User Data to EEMEM9 Store User Data to EEMEM10 Store User Data to EEMEM11 Store User Data to EEMEM12 Store User Data to EEMEM13 Store User Data to EEMEM14 Store User Data to EEMEM15
Table 8. Addresses for Reading (Restoring) RDAC Settings and User Data from EEMEM (R/W = 1, CMD/REG = 0, EE/RDAC = 1)
A4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Data Byte Description Read RDAC0 setting from EEMEM0 Read RDAC1 setting from EEMEM1 Read RDAC2 setting from EEMEM2 Read RDAC3 setting from EEMEM3 Read User Data from EEMEM4 Read User Data from EEMEM5 Read User Data from EEMEM6 Read User Data from EEMEM7 Read User Data from EEMEM8 Read User Data from EEMEM9 Read User Data from EEMEM10 Read User Data from EEMEM11 Read User Data from EEMEM12 Read User Data from EEMEM13 Read User Data from EEMEM14 Read User Data from EEMEM15
RDAC/EEMEM Read
The AD5253/AD5254 provide two different RDAC or EEMEM read operations. For example, Figure 29 shows the method of reading the RDAC0 to RDAC3 contents without specifying the address, assuming address RDAC0 was already selected from the previous operation. If RDAC_N, other than address 0, is selected previously, readback starts with address N, followed by N + 1, and so on. Figure 30 illustrates the random RDAC or EEMEM read operation. This operation allows users to specify which RDAC or EEMEM register is read by first issuing a dummy write command to change the RDAC address pointer, and then proceeding with the RDAC read operation at the new address location.
1
User can store any 64 RDAC settings for AD5253 or 256 RDAC settings for AD5254, not limited to current RDAC wiper setting, directly to EEMEM.
Rev. 0 | Page 16 of 28
AD5253/AD5254
S 0 1 0 1 1 A D 1 A D 0 1 A RDAC_N OR EEMEM_N REGISTER DATA A RDAC_N + 1 OR EEMEM_N + 1 REGISTER DATA A P
SLAVE ADDRESS 1 READ
(N BYTES + ACKNOWLEDGE)
Figure 29. RDAC Current Read. Restricted to Previously Selected Address Stored in the Register.
03842-0-009
S
SLAVE ADDRESS
0
A
INSTRUCTIONAL AND ADDRESS
A
S
SLAVE ADDRESS
1
A
RDAC OR EEMEM DATA
A/A
P
(N BYTES + ACKNOWLEDGE)
0 WRITE
REPEATED START
1 READ
Figure 30. RDAC or EEMEM Random Read
S
0
1
0
1
1
A D 1
A D 0
0
A
CMD/ REG
C 3
C 2
C 1
C 0
A 2
A 1
A 0
A
P
RDAC SLAVE ADDRESS
0 WRITE
1 CMD
Figure 31. RDAC Quick Command Write (Dummy Write)
From Master to Slave
From Slave to Master
S = Start Condition P = Stop Condition A = Acknowledge (SDA Low) A = Not Acknowledge (SDA High) AD1, AD0 = I2C Device Address Bits. Must match with the logic states at Pins AD1, AD0. R/W = Read Enable Bit, Logic High/Write Enable Bit, Logic Low CMD/REG = Command Enable Bit, Logic High/Register Access Bit, Logic Low C3, C2, C1, C0 = Command Bits A2, A1, A0 = RDAC/EEMEM Register Addresses
Table 9. RDAC-to-EEMEM Interface and RDAC Operation Quick Command Bits (CMD/REG = 1, A2 = 0)
C3 0 0 0 0 0 0 0 0 1 1 1 1 1 : 1 C2 0 0 0 0 1 1 1 1 0 0 0 0 1 : 1 C1 0 0 1 1 0 0 1 1 0 0 1 1 0 : 1 C0 0 1 0 1 0 1 0 1 0 1 0 1 0 : 1 Command Description NOP Restore EEMEM (A1, A0) to RDAC (A1, A0)1 Store RDAC (A1, A0) to EEMEM (A1, A0) Decrement RDAC (A1, A0) 6 dB Decrement All RDACs 6 dB Decrement RDAC (A1, A0) One Step Decrement All RDACs One Step Reset: Restore EEMEMs to All RDACs Increment RDACs (A1, A0) 6 dB Increment All RDACs 6 dB Increment RDACs (A1, A0) One Step Increment All RDACs One Step Reserved
Reserved
RDAC/EEMEM Quick Commands
AD5253/AD5254 feature 12 quick commands that facilitate easy manipulation of RDAC wiper settings as well as provide RDAC-to-EEMEM storing and restoring functions. The command format is shown in Figure 31, and the command descriptions are shown in Table 9. When using a quick command, issuing a third byte is not needed but is allowed. The quick commands Reset and Store RDAC to EEMEM require acknowledge polling to determine whether the command has finished executing.
1
This command leaves the device in the EEMEM read power state, which consumes power. Issue the NOP command to return the device to the idle state.
Rev. 0 | Page 17 of 28
03842-0-011
03842-0-010
AD5253/AD5254
Table 10. Address Table for Reading Tolerance (CMD/REG = 0, EE/RDAC = 1, A4 = 1)
A4 1 1 1 1 1 1 1 1 A3 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1
A
A1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1
Data Byte Description Sign and 7-Bit Integer Values of RDAC0 Tolerance (Read Only) 8-Bit Decimal Value of RDAC0 Tolerance (Read Only) Sign and 7-Bit Integer Values of RDAC1 Tolerance (Read Only) 8-Bit Decimal Value of RDAC1 Tolerance (Read Only) Sign and 7-Bit Integer Values of RDAC2 Tolerance (Read Only) 8-Bit Decimal Value of RDAC2 Tolerance (Read Only) Sign and 7-Bit Integer Values of RDAC3 Tolerance (Read Only) 8-Bit Decimal Value of RDAC3 Tolerance (Read Only)
A A
D7 SIGN
D6 26
D5 25
D4 24
D3 23
D2 22
D1 21
D0 20
D7 2-1
D6 2-2
D5 2-3
D4 2-4
D3 2-5
D2 2-6
D1 2-7
D0 2-8
SIGN
7 BITS FOR INTEGER NUMBER
8 BITS FOR DECIMAL NUMBER
Figure 32. Format of Stored Tolerance in Sign Magnitude Format with Bit Position Descriptions. Unit is %. Only Data Bytes Are Shown.
RAB Tolerance Stored in Read-Only Memory
AD5253/AD5254 feature patented RAB tolerances storage in the nonvolatile memory. The tolerance of each channel is stored in the memory during the factory production and can be read by users at any time. The knowledge of the stored tolerance, which is the average of RAB overall codes (Figure 29), allows users to predict RAB accurately. This feature is valuable for precision, rheostat mode, or open-loop applications where knowledge of absolute resistance is critical. The stored tolerances reside in the read-only memory, and are expressed in percent. The tolerance is coded in sign magnitude binary, 16 bits long, and is stored in two memory locations (see Table 10). The data format of the tolerance is the sign magnitude binary format; an example is shown in Figure 32. In the first memory location of the eight data bits, the MSB is designated for the sign (0 = + and 1= -) and the 7 LSBs are designated for the integer portion of the tolerance. In the second memory location, all eight data bits are designated for the decimal portion of tolerance. As shown in Table 8 and Figure 32, for example, if the rated RAB = 10 k and the data readback from address 11000 shows 0001 1100 and address 11001 shows 0000 1111, then RDAC0 tolerance can be calculated as: MSB: 0 = + Next 7 MSB: 001 1100 = 28 8 LSB: 0000 1111 = 15 x 2-8 = 0.06 Tolerance = +28.06% and therefore RAB_ACTUAL = 12.806 k
EEMEM Write-Acknowledge Polling
After each write operation to the EEMEM registers, an internal write cycle begins. The I2C interface of the device is disabled. In order to determine if the internal write cycle is complete and the I2C interface is enabled, interface polling can be executed. I2C interface polling can be conducted by sending a start condition followed by the slave address + the write bit. If the I2C interface responds with an ACK, the write cycle is complete and the interface is ready to proceed with further operations. Otherwise, I2C interface polling can be repeated until it succeeds. Commands 2 and 7 also require acknowledge polling.
EEMEM Write Protection
Setting the WP pin to a logic LOW after EEMEM programming protects the memory and RDAC registers from future write operations. In this mode, the EEMEM and RDAC read operations operate as normal. When write protection is enabled, commands 1 (restore from EEMEM to RDAC) and 7 (reset) function normally to allow RDAC settings to be refreshed from the EEMEM to the RDAC registers.
Rev. 0 | Page 18 of 28
03842-0-012
AD5253/AD5254
I2C COMPATIBLE 2-WIRE SERIAL BUS
1 SCL SDA 0 1 0 1 X 1 AD1 AD0 R/W ACK. BY AD525x X X X X X X X D7 D6 ACK. BY AD525x D5 D4 D3 D2 D1 D0 ACK. BY AD525x STOP BY MASTER 9 1 9 1 9
START BY MASTER
FRAME 1 SLAVE ADDRESS BYTE
FRAME 2 INSTRUCTION BYTE
FRAME 1 DATA BYTE
Figure 33. General I2C Write Pattern
1 SCL SDA 0 1 0 1 1 AD1 AD0 R/W ACK.BY AD525x STARTBY MASTER FRAME1 SLAVE ADDRESS BYTE FRAME 2 RDAC REGISTER D7 D6 D5 D4 D3 D2 D1 D0
03824-0-014
9
1
9
NO ACK.BY MASTER STOP BY MASTER
Figure 34. General I2C Read Pattern
The first byte of the AD5253/AD5254 is a slave address byte (see Figure 24 and Figure 25). It has a 7-bit slave address and an R/W bit. The 5 MSB of the slave address are 01011, and the following 2 LSB are determined by the states of the AD1 and AD0 pins. AD1 and AD0 allow the user to place up to four AD5253/AD5254s on one bus. The 2-wire I2C serial bus protocol operates as follows: AD5253/AD5254 can be controlled via an I2C compatible serial bus, and are connected to this bus as slave device. The 2-wire I2C serial bus protocol follows (see Figure 33 and Figure 34): 1. The master initiates a data transfer by establishing a start condition, such that SDA goes from high to low while SCL is high (Figure 33). The following byte is the slave address byte, which consists of the 5 MSB of a slave address defined as 01011. The next two bits are AD1 and AD0, I2C device address bits. Depending on the states of their AD1 and AD0 bits, four AD5253/AD5254s can be addressed on the same bus. The last LSB, the R/W bit, determines whether data is read from or written to the slave device. The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is called an acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. 2. In the write mode (except when restoring EEMEM to the RDAC register), there is an instruction byte that follows the slave address byte. The MSB of the instruction byte labeled CMD/REG. MSB = 1 enables CMD, the command instruction byte; MSB = 0 enables general register writing. The third MSB in the instruction byte, labeled EE/RDAC, is true only when MSB = 0 or in general writing mode. EE enables the EEMEM register and REG enables the RDAC
Rev. 0 | Page 19 of 28
register. The 5 LSB, A4 to A0, designed the addresses of the EEMEM and RDAC registers; see Figure 27 and Figure 28. When MSB = 1 or when in CMD mode, the four bits following MSB are C3 to C1, which correspond to 12 predefined EEMEM controls and quick commands; there are also four factory reserved commands. The 3 LSB--A2, A1, and A0--are 4-channel RDAC addresses (see Figure 31). After acknowledging the instruction byte, the last byte in the write mode is the data byte. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (Figure 33). 3. In current read mode, the RDAC0 data byte immediately follows the acknowledgment of the slave address byte. After an acknowledgement, RDAC1 follows, then RDAC2, and so on (there is a slight difference in write mode, where the last eight data bits representing RDAC3 data are followed by a no acknowledge bit). Similarly, the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 34). Another reading method, random read method, is shown in Figure 30. When all data bits have been read or written, a stop condition is established by the master. A stop condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition (Figure 33). In read mode, the master issues a no acknowledge for the ninth clock pulse, i.e., the SDA line remains high. The master then brings the SDA line low before the 10th clock pulse, which goes high to establish a stop condition (Figure 34).
4.
03824-0-013
AD5253/AD5254 THEORY OF OPERATION
The AD5253/AD5254 are quad-channel digital potentiometers in 1 k, 10 k, 50 k, or 100 k that allow 64/256 linear resistance step adjustments. The AD5253/AD5254 employ doublegate CMOS EEPROM technology that allows resistance settings and user-defined data stored in the EEMEM registers. The EEMEM is nonvolatile such that settings remain when power is removed. The RDAC wiper settings are restored from the nonvolatile memory settings during device power-up and can also be restored at any time during operation. The AD5253/AD5254 resistor wiper positions are determined by the RDAC register contents. The RDAC register acts like a scratch-pad register, allowing unlimited changes of resistance settings. RDAC register contents can be changed using the device's serial I2C interface. The format of the data-words and the commands to program the RDAC registers are discussed in the I2C Interface section. The four RDAC registers have corresponding EEMEM memory locations that provide nonvolatile storage of resistor wiper position settings. The AD5253/AD5254 provide commands to store the RDAC register contents to their respective EEMEM memory locations. During subsequent power-on sequences, the RDAC registers are automatically loaded with the stored value. Whenever the EEMEM write operation is enabled, the device activates the internal charge pump and raises the EEMEM cell gate bias voltage to a high level; this essentially erases the current content in the EEMEM register and allows subsequent storage of the new content. Saving data to an EEMEM register consumes about 35 mA of current and lasts approximately 26 ms. Because of charge pump operation, all RDAC channels may experience noise coupling during the EEMEM writing operation. The EEMEM restore time in power-up or during operation is about 300 s. Note that the power-up EEMEM refresh time depends on how fast VDD reaches its final value. As a result, any supply voltage decoupling capacitors limit the EEMEM restore time during power-up. Figure 20 shows the power-up profile where VDD, without any decoupling capacitors connected to it, is applied with a digital signal. The device initially resets the RDACs to midscale before restoring the EEMEM contents. In addition, users should issue a NOP command 0 immediately after using command 1 to restore the EEMEM setting to RDAC, thereby minimizing supply current dissipation. Reading user data directly from EEMEM does not require a similar NOP command execution. In addition to the movement of data between RDAC registers and EEMEM memory, the AD5253/AD5254 provide other shortcut commands that facilitate the user's programming needs, as shown in Table 11.
Rev. 0 | Page 20 of 28
Table 11. AD5253/AD5254 Quick Commands
Commmand 0 1 Description NOP. Restore EEMEM Content to RDAC. User should issue NOP immediately after this command to conserve power. Store RDAC Register Setting to EEMEM. Decrement RDAC 6 dB (Shift Data Bits Right). Decrement All RDACs 6 dB (Shift All Data Bits Right). Decrement RDAC One Step. Decrement All RDACs One Step. Reset EEMEM Contents to All RDACs. Increment RDAC 6 dB (Shift Data Bits Left). Increment All RDACs 6 dB (Shift All Data Bits Left). Increment RDAC One Step. Increment All RDACs One Step. Reserved.
2 3 4 5 6 7 8 9 10 11 12-15
LINEAR INCREMENT AND DECREMENT COMMANDS
The increment and decrement commands (#10, #11, #5, #6) are useful for linear step adjustment applications. These commands simplify microcontroller software coding by allowing the controller to send just an increment or decrement command to the AD5253/AD5254. The adjustments can be directed to a single RDAC or to all four RDACs.
6 dB ADJUSTMENTS (DOUBLING/HALVING WIPER SETTING)
The AD5253/AD5254 accommodate 6 dB adjustments of the RDAC wiper positions by shifting the register contents to left/ right for increment/decrement operations, respectively. Commands 3, 4, 8, and 9 can be used to increment or decrement the wiper positions in 6 dB steps synchronously or asynchronously. Incrementing the wiper position by +6 dB is essentially doubling the RDAC register value, while decrementing by -6 dB is halving the register content. Internally, the AD5253/AD5254 use shift registers to shift the bits left and right to achieve a 6 dB increment or decrement. The maximum number of adjustments is nine and eight steps for increment from zero scale and decrement from full scale, respectively. These functions are useful for various audio/video level adjustments, especially white LED brightness settings where the visual responses of humans are more sensitive to large rather small adjustments.
AD5253/AD5254
DIGITAL INPUT/OUTPUT CONFIGURATION
SDA is a digital input/output with an open-drain MOSFET that requires a pull-up resistor for proper communication. On the other hand, SCL and WP are digital inputs with pull-up resistors recommended to minimize the MOSFET crossconduction when the driving signals are lower than VDD. SCL and WP have ESD protection diodes, as shown in Figure 35 and Figure 36. WP can be permanently tied to VDD without a pull-up resistor if the write-protect feature is not used. If WP is left floating, an internal current source will pull it low to enable write-protect. In applications where the device is not being programmed on a frequent basis, this allows the part to default to write-protect after any one-time factory programming or field calibration without using an on-board pull-down resistor. Since there are protection diodes on all these inputs, their signal levels must not be greater than VDD to prevent forward biasing of the diodes.
VDD
MULTIPLE DEVICES ON ONE BUS
AD5253/AD5254 are equipped with two addressing pins, AD1 and AD0, that allow up to four AD5253/AD5254s to be operated on one I2C bus. To achieve this result, the states of AD1 and AD0 on each device must first be defined. An example is shown in Table 12 and Figure 37. In I2C programming, each device is issued a different slave address--01011(AD1)(AD0)-- to complete the addressing. Table 12. Multiple Devices Addressing
AD1 0 0 1 1 AD0 0 1 0 1 Device Addressed U1 U2 U3 U4
+5V RP RP
SDA MASTER VDD SDA SCL AD1 U1 AD0 SDA SCL AD1 U2 AD0 VDD SDA SCL AD1 U3 AD0 VDD SDA SCL AD1 U4 AD0 SCL
SCL
03824-0-035
Figure 37. Multiple AD5253/AD5254s on a Single Bus
GND
Figure 35. SCL Digital Input
VDD
INPUTS
WP
GND
Figure 36. Equivalent WP Digital Input
In wireless base station smart antenna systems where arrays of digital potentiometers may be needed to bias the power amplifiers, large numbers of AD5253/AD5254s can be addressed by using extra decoders, switches, and I/O buses, as shown in Figure 38. For example, to communicate to a total of 16 devices, four decoders and 16 sets of combinational switches (four sets shown in Figure 36) are needed. Two I/O buses serve as the common inputs of the four 2 x 4 decoders and select four sets of outputs at each combination. Because the four sets of combination switch outputs are unique, as shown in Figure 38, a specific device is addressed by proper I2C programming with the slave address defined as 01011(AD1)(AD0). This operation allows one out of 16 devices to be addressed, provided the inputs of the two decoders do not change states. The decoders' inputs are allowed to change once the operation of the specified device is completed.
03824-0-036
Rev. 0 | Page 21 of 28
03824-0-037
AD5253/AD5254
+5V x4 AD1 2 2x4 DECODER 4 N1 AD0
VDD
R1
A W B
+5V
03824-0-039
03824-0-040
R2X
x4 AD1
VSS
2x4 DECODER
4
N2X +5
Figure 39. Maximum Terminal Voltages Set by VDD and VSS
POWER-UP AND POWER-DOWN SEQUENCES
AD0
P2Y P2Y
2x4 DECODER
4
+5V x4 P3X R3X R3Y AD0 N3Y AD1
Since the ESD protection diodes limit the voltage compliance at terminals A, B, and W (Figure 39), it is important to power VDD/VSS before applying any voltage to terminals A, B, and W. Otherwise, the diodes are forward-biased such that VDD/VSS are powered unintentionally and may affect the rest of the user's circuit. Similarly, VDD/VSS should be powered down last. The ideal power-up sequence is in the following order: GND, VDD, VSS, digital inputs, and VA/VB/VW. The order of powering VA, VB, VW, and the digital inputs is not important, as long as they are powered after VDD/VSS.
LAYOUT AND POWER SUPPLY BIASING
It is always a good practice to employ a compact, minimum lead-length layout design. The leads to the input should be as direct as possible, with a minimum conductor length. Ground paths should have low resistance and low inductance.
2x4 DECODER
4
+5V x4 P4 R4 AD1 AD0
03824-0-038
Figure 38. Four Devices with AD1 and AD0 of 00
Similarly, it is also good practice to bypass the power supplies with quality capacitors. Low ESR (equivalent series resistance) 1 F to 10 F tantalum or electrolytic capacitors should be applied at the supplies to minimize any transient disturbance and filter low frequency ripple. Figure 40 illustrates the basic supply-bypassing configuration for the AD5253/AD5254.
AD5253/AD5254
VDD C3 C1 10F C4 VSS C2 10F 0.1F VSS GND 0.1F VDD
TERMINAL VOLTAGE OPERATION RANGE
The AD5253/AD5254 are designed with internal ESD diodes for protection; these diodes also set the boundary of the terminal operating voltages. Positive signals present on terminal A, B, or W that exceed VDD are clamped by the forward biased diode. Similarly, negative signals on terminal A, B, or W that are more negative than VSS are also clamped (see Figure 39). In practice, users should not operate VAB, VWA, and VWB to be higher than the voltage across VDD-to-VSS, but VAB, VWA, and VWB have no polarity constraint.
Figure 40. Power Supply Bypassing
The ground pin of the AD5253/AD5254 is used primarily as a digital ground reference. To minimize the digital ground bounce, the AD5253/AD5254 ground terminal should be joined remotely to the common ground (see Figure 40).
Rev. 0 | Page 22 of 28
AD5253/AD5254
DIGITAL POTENTIOMETER OPERATION
The structure of the RDAC is designed to emulate the performance of a mechanical potentiometer. The RDAC contains a string of resistor segments, with an array of analog switches acting as the wiper connection to the resistor array. The number of points is the resolution of the device. For example, the AD5253/AD5254 emulates 64/256 connection points with 64/256 equal resistance, RS, allowing it to provide better than 1.5%/0.4% settability resolution. Figure 41 provides an equivalent diagram of the connections between the three terminals that make up one channel of the RDAC. Switches SWA and SWB are always ON, while one of switches SW(0) to SW(2N-1) is ON one at a time, depending on the setting decoded from the data bit. Since the switches are nonideal, there is a 75 wiper resistance, RW. Wiper resistance is a function of supply voltage and temperature; lower supply voltages and higher temperatures result in higher wiper resistances. Consideration of wiper resistance dynamics is important in applications where accurate prediction of output resistance is required.
SWA AX
PROGRAMMABLE RHEOSTAT OPERATION
If either the W-to-B or W-to-A terminal is used as a variable resistor, the unused terminal can be opened or shorted with W; such operation is called rheostat mode (see Figure 42). The resistance tolerance can range 20%.
A A A
W B B
W B
W
Figure 42. Rheostat Mode Configuration
SW (2N - 1)
The nominal resistance of the AD5253/AD5254 has 64/256 contact points accessed by the wiper terminal, plus the B terminal contact. The 6-/8-bit data-word in the RDAC register is decoded to select one of the 64/256 settings. The wiper's first connection starts at the B terminal for data 0x00. This B terminal connection has a wiper contact resistance, RW, of 75 , regardless of the nominal resistance. The second connection (AD5253 10 k part) is the first tap point where RWB = 231 [RWB =RAB/64 + RW = 156 + 75 ] for data 0x01, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at RWB = 9893 . See Figure 41 for a simplified diagram of the equivalent RDAC circuit. The general equation that determines the digitally programmed output resistance between W and B, is RWB(D) = (D/64) x RAB + 75 (AD5253) RWB(D) = (D/256) x RAB + 75 (AD5254) (1) (2)
RDAC WIPER REGISTER AND DECODER
WX RS SW (2N - 2)
RS SW(1)
Where D is the decimal equivalent data contained in the RDAC latch, and RAB is the nominal end-to-end resistance.
RS RS = RAB/2N DIGITAL CIRCUITRY OMIITTED FOR CLARITY
SW(0)
100
SWB BX
RWA
03824-0-041
RWB
75
Figure 41. Equivalent RDAC Structure
(%)
50
25
0
10
32 D (Code in Decimal)
48
63
Figure 43. AD5253 RWA(D) and RWB(D) vs. Decimal Code
Rev. 0 | Page 23 of 28
03824-0-043
0
03824-0-042
AD5253/AD5254
For example, the RWB values shown in Table 13 can be found on AD5253 10 k parts. Table 13. RWB vs. Codes; RAB = 10 k, A terminal = Open
D (DEC) 63 32 1 0 RWB () 9918 5075 231 75 Output State Full Scale Midscale 1 LSB Zero Scale (Wiper Resistance)
PROGRAMMABLE POTENTIOMETER OPERATION
If all three terminals are used, the operation is called potentiometer mode and the most common configuration is the voltage divider operation (see Figure 44).
VI A
W B
Note that in the zero-scale condition, a 75 finite wiper resistance is present. Care should be taken to limit the current conduction between W and B in this state to no more than 5 mA continuous for a total resistance of 1 k, or a 20 mA pulse, to avoid degradation or possible destruction of the internal switch contact. Similar to the mechanical potentiometer, the resistance of the RDAC between wiper W and terminal A also produces a digitally controlled complementary resistance, RWA. When these terminals are used, the B terminal can be opened. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value (see Figure 41). The general equation for this operation is RWA(D) = [(64 - D)/64] x RAB + 75 (AD5253) RWA(D) = [(256 - D)/256] x RAB + 75 (AD5254) Table 14. RWA vs. Codes; AD5253, RAB = 10 k, B terminal = Open
D (DEC) 63 32 1 0 RWA () 231 5075 9918 10075 Output State Full-Scale Midscale 1 LSB Zero-Scale
Figure 44. Potentiometer Mode Configuration
If the wiper resistance is ignored, the transfer function is simply
VW =
VW =
D x V AB + V B (AD5253) 64
D x V AB + V B (AD5254) 256
03824-0-044
VC
(5)
(6)
A more accurate calculation, which includes the wiper resistance effect, yields
D R AB + RW N VA VW (D ) = 2 R AB + 2RW
(7)
(3) (4)
Where 2N is the number of steps. Unlike in rheostat mode operation where the tolerance is high, potentiometer mode operation yields an almost ratiometric function of D/2N with a relatively small error contributed by the RW terms. Therefore, the tolerance effect is almost cancelled. Similarly, the ratiometric adjustment also reduces the temperature coefficient effect to 50 ppm/C, except at low value codes where RW dominates. Potentiometer mode operations include other applications such as op amp input, feedback resistor networks, and other voltage scaling applications. The A, W, and B terminals can in fact be input or output terminals, provided |VA|, |VW|, and |VB| do not exceed VDD-to-VSS.
The typical distribution of RAB from channel-to-channel matches is about 0.15% within a given device. On the other hand, device-to-device matching is process lot dependent with a 20% tolerance.
Rev. 0 | Page 24 of 28
AD5253/AD5254 APPLICATIONS
RGB LED LCD BACKLIGHT CONTROLLER
High power (>1 W) RGB LEDs have been improved so dramatically in efficiency and cost that they are likely to replace CCFLs (cold cathode florescent lamps) as backlighting sources in high end LCD panels in the near future. Unlike conventional LEDs, high power LEDs have a forward voltage of 2 V to 4 V, and consume more than 350 mA at maximum brightness. The LED brightness is a linear function of the conduction current but not the forward voltage. To increase brightness of a given color, multiple LEDs can be connected in series, rather than in parallel, to achieve uniform brightness. For example, three red LEDs configured in series require an average of 6 V to 12 V voltage headroom, but the circuit operation requires current control. As a result, Figure 45 shows the implementation of one high power RGB LED controller using a digital potentiometer AD5254, a boost regulator, an op amp, and power MOSFETs. The ADP1610 (U2 in Figure 45) is an adjustable boost regulator with its output adjusted by the AD5254's RDAC3. Such an output should be set high enough for proper operation but low enough to conserve power. The ADP1610's 1.2 V band gap reference is buffered to provide the reference level for the voltage dividers set by the AD5254's RDAC0 to RDAC2 and resistors R2 to R4. For example, by adjusting the AD5254's RDAC0, the desirable voltage appears across the sense resistors, RR. If U2's output is set properly, op amp U3A and power MOSFET N1 do whatever is necessary to regulate the current of the loop. As a result, the current through the sense resistor and the red LEDs is
IR = V RR RR
(8)
R8 is needed to prevent oscillation. In addition to the 256 levels of adjustable current/brightness, users may also apply a PWM signal at U3's SD pin to achieve finer brightness resolution or better power efficiency.
Rev. 0 | Page 25 of 28
AD5253/AD5254
+5V C10 10F R6 R7 RDAC3 22k 22k U3D AD8594 R4 R3 R2 250k 250k 250k RDAC2 10k B2 SCL SDA VREF = 2.5V 10k CLK SDI B3 RC 100k CC U1 VDD C1 0.1F A3 R1 R5 10k 10k U2 IN L1 10F D1 C3 10F DB1 DB2 +5V C11 8 W2 0.1F N3 R10 4.7 IRFL3103 IG VB IB DB3 DG1 DG2 DG3 VOUT DR1 DR2 DR3
ADP1610
SW FB SD COMP SS RT GND CSS 10F
AD5254
A2
390F
U3C V+ AD8594 V- 4
VRB A1 RDAC1 10k B1 W1 AD8594 4.7 IRFL3103 VRG 0.1 N1 R8 AD8594 4.7 VSS GND AD0 AD1 RR PWM SD 0.1
03824-0-045
VG U3B RB R9 IR 0.1 N2
A0 RDAC0 L1 - SLF6025-100M1R0 D1 - MBR0520LT1 10k B0 W0
U3A
RG
VR
IRFL3103 VRR
Figure 45. Digital Potentiometer-Based RGB LED Controller
Rev. 0 | Page 26 of 28
AD5253/AD5254 OUTLINE DIMENSIONS
6.60 6.50 6.40
20
11
4.50 4.40 4.30 6.40 BSC
1 10
PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX 0.20 0.09 8 0 0.75 0.60 0.45
SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-153AC
Figure 46. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters
ORDERING GUIDE
Model AD5253BRU1 AD5253BRU1-RL7 AD5253BRU10 AD5253BRU10-RL7 AD5253BRU50 AD5253BRU50-RL7 AD5253BRU100 AD5253BRU100-RL7 AD5253EVAL AD5254BRU1 AD5254BRU1-RL7 AD5254BRU10 AD5254BRU10-RL7 AD5254BRU50 AD5254BRU50-RL7 AD5254BRU100 AD5254BRU100-RL7 AD5254EVAL Step 64 64 64 64 64 64 64 64 64 256 256 256 256 256 256 256 256 256 RAB (k) 1 1 10 10 50 50 100 100 10 1 1 10 10 50 50 100 100 10 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Evaluation Board Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Evaluation Board Package Option RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 Full Container Quantity 75 1,000 75 1,000 75 1,000 75 1,000 1 75 1,000 75 1,000 75 1,000 75 1,000 1
Rev. 0 | Page 27 of 28
AD5253/AD5254 NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03824-0-4/04(0)
Rev. 0 | Page 28 of 28

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